2006
An Image Processing Pipeline with Digital Compensation of Low Cost Optics for Mobile Telephony
International Conference on Multimedia and Expo (ICME). July 2006. Toronto, Canada.
Reconfigurable Streaming Architectures for Embedded Smart Cameras Applications
2nd IEEE Workshop on Embedded Computer Vision, in conjunction with CVPR. June 2006. New York, NY.
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
3th Reconfigurable Architectures Workshop (RAW). April 2006. Rhodes Island, Greece.
Template-Based Generation of Streaming Accelators from a High Level Presentation
International Symposium on Field-Programmable Custom Computing Machines (FCCM). April 2006. Napa Valley, CA.
Stream Memory Subsystem in Reconfigurable Platforms
2nd Workshop on Architecture Research using FPGA Platforms (WARFP). February 2006. Austin, TX.
2005
A Low - Power VLSI Architecture for Intra Prediction in H.264
10th Panhellenic Conference on Informatics (PCI). November 2005. Volos, Greece.
2003
A programmable, high performance vector array unit used for real-time motion estimation
Proceedings of the International Conference on Multimedia and Expo (ICME). July 2003. Baltimore, MD.
2000
Using dynamic cache management techniques to reduce energy in general purpose processors
ΙΕEE Transactions on VLSI Systems. December 2000.
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on VLSI Systems. Special Issue on Low Power. June 2000.
1999
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache
Proceedings of the International Symposium on Computer Design (ICCD). October 1999. Austin, TX.
Using dynamic cache management techniques to reduce energy in a high-performance processor
International Symposium of Low Power Electronics and Design (ISLPED). August 1999. San Diego, CA.
An analytical, transistor-level energy model for SRAM-based caches
International Symposium of Circuits and Systems (ISCAS). June 1999. Orlando, FL.
1998
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors
Proceedings of the International Symposium of Low Power Electronics and Design (ISLPED). August 1998. Monterey, CA.
1996
Algorithm-based error-detection schemes for iterative solution of partial differential equations
IEEE Transactions on Computers. April 1996.
Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations
IEEE Trans. Computers. .
1993
A new scheme for I-Cache energy reduction in High Performance Processors
Power-Driven Microarchitecture Workshop, International Symposium On Computer Architecture (ISCA). June 1998. Barcelona, Spain.