N. Bellas, Hajj, I. N., and Polychronopoulos, C. D., “An analytical, transistor-level energy model for SRAM-based caches”, International Symposium of Circuits and Systems (ISCAS), 06 vol. Orlando, FL, pp. 198-201, 1999, doi: 10.1109/ISCAS.1999.780129.
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