2005
smt-SPRINTS: Software Precomputation with Intelligent Streaming for Resource-Constrained SMTs
11th International Euro-Par Conference. August 2005. Lisbon, Portugal.
An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors
First International Workshop on OpenMP Shared Memory Parallel Programming (IWOMP). June 2005. Eugene, OR.
Multigrain parallel Delaunay Mesh generation: challenges and opportunities for multithreaded architectures
19th Annual International Conference on Supercomputing (ICS). June 2005. Cambridge, MA.
Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
19th International Parallel and Distributed Processing Symposium (IPDPS). April 2005. Denver, CO.
2004
Realistic Workload Scheduling Policies for Taming the Memory Bandwidth Bottleneck of SMPs
11th International Conference on High Performance Computing (HiPC). December 2004. Bangalore, India.
Dynamic page migration in software DSM systems
IEEE International Conference on Cluster Computing (CLUSTER). September 2004. San Diego, CA.
2003
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
32nd International Conference on Parallel Processing (ICPP). October 2003. Kaohsiung, Taiwan.
A programmable, high performance vector array unit used for real-time motion estimation
Proceedings of the International Conference on Multimedia and Expo (ICME). July 2003. Baltimore, MD.
2001
Informing Algorithms for Efficient Scheduling of Synchronizing Threads on Multiprogrammed SMPs
Proceedings of the 2001 International Conference on Parallel Processing (ICPP). September 2001. Valencia, Spain.
2000
Using dynamic cache management techniques to reduce energy in general purpose processors
ΙΕEE Transactions on VLSI Systems. December 2000.
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on VLSI Systems. Special Issue on Low Power. June 2000.
Efficient Dynamic Parallelism with OpenMP on Linux SMPs
International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA). June 2000. Las Vegas, NV.
1999
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache
Proceedings of the International Symposium on Computer Design (ICCD). October 1999. Austin, TX.
Using dynamic cache management techniques to reduce energy in a high-performance processor
International Symposium of Low Power Electronics and Design (ISLPED). August 1999. San Diego, CA.
Achieving multiprogramming scalability of parallel programs on Intel SMP platforms: Nanothreading in the Linux kernel
Proceedings of the Conference on Parallel Computing (ParCo). August 1999. Delft, The Netherlands.
An analytical, transistor-level energy model for SRAM-based caches
International Symposium of Circuits and Systems (ISCAS). June 1999. Orlando, FL.
1998
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors
Proceedings of the International Symposium of Low Power Electronics and Design (ISLPED). August 1998. Monterey, CA.
1996
Algorithm-based error-detection schemes for iterative solution of partial differential equations
IEEE Transactions on Computers. April 1996.
Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations
IEEE Trans. Computers. .
1993
A new scheme for I-Cache energy reduction in High Performance Processors
Power-Driven Microarchitecture Workshop, International Symposium On Computer Architecture (ISCA). June 1998. Barcelona, Spain.
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