2010
Fisheye lens distortion correction on multicore and hardware accelerator platforms
24th International Parallel and Distributed Processing Symposium (IPDPS). April 2010. Atlanta, GA.
2009
Proteus: An architectural synthesis tool based on the stream programming paradigm
19th International Conference on Field Programmable Logic and Applications (FPL). August 2009. Prague, The Czech Republic.
Mapping the AVS Video Decoder on a Heterogeneous Dual-Core SIMD Processor
46th Design Automation Conference (DAC)-User Track. July 2009. San Francisco, CA.
Extending a Stream Programming Paradigm to Hardware Accelerator Platforms
Symposium on Application Accelerators for High Performance Computing (SAAHPC 2009). July 2009. Champaign, IL.
Implementation of a wide-angle lens distortion correction algorithm on the cell broadband engine
23rd International Conference on Supercomputing (ICS). June 2009. New York Metro Area, NY.
Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). April 2009. Napa Valley, CA.
2008
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators
IEEE Trans. on CAD of Integrated Circuits and Systems. .
2007
Mapping streaming architectures on reconfigurable platforms
ACM SIGARCH Computer Architecture News. June 2007.
An Architectural Framework for Automated Streaming Kernel Selection
14th Reconfigurable Architectures Workshop (RAW). March 2007. Long Beach, CA.
2006
Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators
ΙΕEE Transactions on Computer-Aided Design (TCAD). August 2006. Madrid, Spain.
Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs
16th International Conference on Field Programmable Logic and Applications (FPL). August 2006. Madrid, Spain.
An Image Processing Pipeline with Digital Compensation of Low Cost Optics for Mobile Telephony
International Conference on Multimedia and Expo (ICME). July 2006. Toronto, Canada.
Reconfigurable Streaming Architectures for Embedded Smart Cameras Applications
2nd IEEE Workshop on Embedded Computer Vision, in conjunction with CVPR. June 2006. New York, NY.
Template-Based Generation of Streaming Accelators from a High Level Presentation
International Symposium on Field-Programmable Custom Computing Machines (FCCM). April 2006. Napa Valley, CA.
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
3th Reconfigurable Architectures Workshop (RAW). April 2006. Rhodes Island, Greece.
Stream Memory Subsystem in Reconfigurable Platforms
2nd Workshop on Architecture Research using FPGA Platforms (WARFP). February 2006. Austin, TX.
2005
A Low - Power VLSI Architecture for Intra Prediction in H.264
10th Panhellenic Conference on Informatics (PCI). November 2005. Volos, Greece.
2003
A programmable, high performance vector array unit used for real-time motion estimation
Proceedings of the International Conference on Multimedia and Expo (ICME). July 2003. Baltimore, MD.
2000
Using dynamic cache management techniques to reduce energy in general purpose processors
ΙΕEE Transactions on VLSI Systems. December 2000.
Architectural and compiler techniques for energy reduction in high-performance microprocessors
IEEE Transactions on VLSI Systems. Special Issue on Low Power. June 2000.