Τhe Impact of CPU Voltage Margins on Power-Constrained Execution

The manuscript by Panos Koutsovasilis and members of the CSL team and the University of Athens, titled “The Impact of CPU Voltage Margins on Power-Constrained Execution” was accepted for publication at the IEEE Transactions on Sustainable Computing (IEEE TSUSC). Online publication was in December 2020.

This work investigates the impact of reducing voltage margins beyond the nominal level on the efficiency of CPU power capping mechanisms, for three commercial systems, two Applied Micro ARMv8 micro-servers (X-Gene2 and X-Gene3) and an Intel x86-64 (Xeon E3).