N. Bellas, Hajj, I. N., Polychronopoulos, C. D., and Stamoulis, G. D., “Energy and Performance Improvements in Microprocessor Design Using a Loop Cache”, Proceedings of the International Symposium on Computer Design (ICCD), 10 vol. Austin, TX, pp. 378-383, 1999, doi: 10.1109/ICCD.1999.808570.
N. Bellas, Hajj, I. N., and Polychronopoulos, C. D., “An analytical, transistor-level energy model for SRAM-based caches”, International Symposium of Circuits and Systems (ISCAS), 06 vol. Orlando, FL, pp. 198-201, 1999, doi: 10.1109/ISCAS.1999.780129.
N. Bellas, Hajj, I. N., and Polychronopoulos, C. D., “Using dynamic cache management techniques to reduce energy in a high-performance processor”, International Symposium of Low Power Electronics and Design (ISLPED), 08 vol. San Diego, CA, pp. 64-69, 1999, doi: 10.1145/313817.313856.
N. Bellas, Hajj, I. N., Stamoulis, G. D., and Polychronopoulos, C. D., “Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors”, Proceedings of the International Symposium of Low Power Electronics and Design (ISLPED), 08 vol. Monterey, CA, pp. 70-75, 1998, doi: 10.1145/280756.280788.
V. Vassiliadis et al., “A programming model and runtime system for significance-aware energy-efficient computing”, ACM 20th Symposium on Principles and Practice of Parallel Programming (PPoPP), 02 vol. San Francisco, CA, pp. 275-276, 2015, doi: 10.1145/2688500.2688546.
M. Spyrou et al., “Energy Minimization on Heterogeneous Systems through Approximate Computing”, International Conference on Parallel Computing (PARCO), 09 vol. Edinburgh, UK, pp. 741-752, 2015, doi: 10.3233/978-1-61499-621-7-741.
D. S. Nikolopoulos et al., “Energy Efficiency through Significance-Based Computing”, IEEE Computer, vol. 47, 07 vol., Art. no. 7, 2014, doi: 10.1109/MC.2014.182.
G. Karakonstantis, Bellas, N., Antonopoulos, C. D. D., Tziantzioulis, G., Gupta, V., and Roy, K., “Significance driven computation on next-generation unreliable platforms”, Design Automation Conference (DAC), Wild And Crazy Ideas Session (WACI), 06 vol. San Diego, CA, pp. 290-291, 2011, doi: 10.1145/2024724.2024794.
C. Kalogirou et al., “Exploiting CPU Voltage Margins to Increase the Profit of Cloud Infrastructure Providers”, 2019 19th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGRID), 05 vol. IEEE, Larnaca, Cyprus, pp. 302-311, 2019, doi: 10.1109/CCGRID.2019.00044.
P. K. Koutsovasilis, Kalogirou, C., Konstantas, C., Maroudas, E., Spyrou, M., and Antonopoulos, C. D. D., “AcHEe: Evaluating approximate computing and heterogeneity for energy efficiency”, Parallel Computing, vol. 73, 04 vol., 2018, doi: 10.1016/j.parco.2017.03.002.