N. Bellas, Hajj, I. N., Polychronopoulos, C. D., and Stamoulis, G. D., “A new scheme for I-Cache energy reduction in High Performance Processors”, Power-Driven Microarchitecture Workshop, International Symposium On Computer Architecture (ISCA), 06 vol. Barcelona, Spain, 1993.
A. Diavastos and Antonopoulos, C. D. D., “Facilitating Widespread Adoption of Edge Computing through Development of a Universal Microserver Architecture and Software Ecosystem”, International Conference on High Performance Embedded Architectures and Compilers, (HiPEAC). Poster presentation, 01 vol. Manchester, UK, 2018.
C. Kalogirou, Antonopoulos, C. D. D., Bellas, N., Lalis, S., Mukhanov, L., and Karakonstantis, G., “Increasing the Profit of Cloud Providers through DRAM Operation at Reduced Margins”, 2020 20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGRID), 05 vol. IEEE, Virtual Conference, 2020, doi: 10.1109/ccgrid49817.2020.00-38.
P. Koutsovasilis, Parasyris, K., Antonopoulos, C. D. D., Bellas, N., and Lalis, S., “Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs”, IEEE Transactions on Parallel and Distributed Systems, vol. 31, 12 vol., no. 12, 2020, doi: 10.1109/tpds.2020.3004383.
N. Bellas, Hajj, I. N., Polychronopoulos, C. D., and Stamoulis, G. D., “Energy and Performance Improvements in Microprocessor Design Using a Loop Cache”, Proceedings of the International Symposium on Computer Design (ICCD), 10 vol. Austin, TX, pp. 378-383, 1999, doi: 10.1109/ICCD.1999.808570.
N. Bellas, Hajj, I. N., and Polychronopoulos, C. D., “An analytical, transistor-level energy model for SRAM-based caches”, International Symposium of Circuits and Systems (ISCAS), 06 vol. Orlando, FL, pp. 198-201, 1999, doi: 10.1109/ISCAS.1999.780129.
N. Bellas, Hajj, I. N., and Polychronopoulos, C. D., “Using dynamic cache management techniques to reduce energy in a high-performance processor”, International Symposium of Low Power Electronics and Design (ISLPED), 08 vol. San Diego, CA, pp. 64-69, 1999, doi: 10.1145/313817.313856.
N. Bellas, Hajj, I. N., Stamoulis, G. D., and Polychronopoulos, C. D., “Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors”, Proceedings of the International Symposium of Low Power Electronics and Design (ISLPED), 08 vol. Monterey, CA, pp. 70-75, 1998, doi: 10.1145/280756.280788.
M. Curtis-Maury, Dzierwa, J., Antonopoulos, C. D. D., and Nikolopoulos, D. S., “Online power-performance adaptation of multithreaded programs using hardware event-based prediction”, Proceedings of the 20th Annual International Conference on Supercomputing (ICS), 06 vol. Cairns, Queensland, Australia, pp. 157-166, 2006, doi: 10.1145/1183401.1183426.
M. Curtis-Maury, Dzierwa, J., Antonopoulos, C. D. D., and Nikolopoulos, D. S., “Online strategies for high-performance power-aware thread execution on emerging multiprocessors”, 20th International Parallel and Distributed Processing Symposium (IPDPS), 04 vol. Rhodes Island, Greece, 2006, doi: 10.1109/IPDPS.2006.1639598.